The invention relates generally to automated design analysis and more particularly to a tool for generating organized high level schematics from the transistor images of a die.
In the intensely competitive field of microelectronics, detailed analysis of a semiconductor integrated circuit product can provide valuable information as to how a particular technical problem was addressed, overall strengths and weaknesses of a design approach, and such matters. This information can be used to make decisions regarding market positioning, future designs, and new product development. The information produced from analysis of the product is typically provided through circuit extraction (reverse engineering), functional analysis, and other technical means. At the core of this activity is the process of design analysis which, in this context, refers to the techniques and methodology used to derive a complete or partial set of schematics from any type of integrated circuit manufactured using any process technology. For such technical information to be of strategic value it must be accurate and cost effective, and it is very important that the information should generated in a timely manner.
A design analysis process typically involves skilled engineers manually extracting circuit information from a set of large xe2x80x9cphotomosaicsxe2x80x9d of an integrated circuit (IC). Skilled technicians and engineers perform the following sequential tasks:
(1) A high magnification image of a small portion of an IC is captured using a camera or electron microscope such as a SEM. The IC has been processed to expose a layer of interest.
(2) Step (1) is repeated for all of the various regions of interest of the layer of the IC, ensuring that sufficient overlap exists between adjacent images that will be used to create the photomosaics.
(3) Create Photomosaics: all adjacent photographs associated with the given IC layer are aligned and taped together.
(4) Steps (1)-(3) are repeated for every layer necessary to construct a layout database of the IC. All layers include interconnect layers. For example, four sets of photomosaics are required for a device with three layers of metal and one layer of polysilicon.
(5) Circuit Extraction: transistors, logic gates, and other elements employed in the IC are identified by manually, visually examining the polysilicon and lower metal interconnects photomosaics. Interconnections between circuit elements are traced and this information is captured in the form of schematic drawings. The drawings are manually checked against the photomosaics and any obvious errors are corrected.
(6) Organize Schematics: the schematic drawings are organized into hierarchical functional/logical blocks.
(7) Capture Schematics: the schematic drawings are entered into a computer using computer aided engineering (CAE) software tools for subsequent simulation and functional analysis of the IC.
The results of these substantially manual techniques for circuit extraction are often difficult to analyze. Difficulties arise in tracing signals that travel between several schematics. Locating the schematics associated with a particular signal can be very time consuming. During the circuit extraction process, signals are commonly given a generic name or label as a reference. Further analysis will reveal the purpose or function of these signals. The signals should then be renamed so that their name indicates their function. The signal renaming process creates two problems. Firstly, it takes some time to locate each schematic associated with a particular signal such that the signal can be relabeled on each schematic where it appears. Secondly, guaranteeing that the signal has been renamed on each schematic is difficult. This can result in inconsistencies with signal names that can confuse the engineer attempting to analyze the circuitry.
Another time consuming task associated with this manual circuit extraction process is the creation of signal and schematic lists. It is often useful to have a cross-reference between signal names and the name or number of the schematic in which these signals appear. However, such a cross-reference is very labor intensive to produce.
Once the schematics have been entered into a computer for simulation and/or subsequent analysis, it becomes difficult to edit the schematics. For example, as the circuit analysis progresses, it frequently becomes necessary to redraw certain schematics or to transfer portions of one schematic to another. Editing a set of schematics in such a way can often cause errors in the net list which require manual correction. Signal names and other labels on the revised schematics will also have to be manually changed.
Other than the manual method described above, the design analysis process can alternatively employ an automated circuit extraction process such as the one described in U.S. Pat. No. 5,694,481 which issued on Dec. 2, 1997 to Lam et al. Lam discloses an automated system for extracting design information from a semiconductor integrated circuit by imaging layers of an IC, creating a mosaic of the images, identifying the circuit elements, developing a basic net list of the circuit element connections, organizing the net list into functional blocks, and generating schematic diagrams.
Unfortunately, the circuit extraction method disclosed by Lam has the same restrictions as the manual method when in comes to locating signals and schematics, creating signal and schematic lists, and editing existing schematics. In fact, the automated method adds the burden of identifying logic gates and standard cells from a randomly organized net list. An engineer is required to sort through the schematics to convert the connected transistors into the relevant logic gates and standards cells. Obviously, this can take a very long period of time.
The results of these substantially manual techniques for circuit extraction are difficult to analyze since the resulting schematics are difficult to follow.
Therefore, there is a need for a tool to generate organized schematics at such a level that they may be properly and efficiently analysed as to their functionality.
The invention is directed to a process in a computer system for generating a high level schematic from a project schematic of basic components which comprises scanning the project schematic for a predetermined cell, wherein the cell is made up of a select group of components and their interconnections, and replacing the select group of components on every occurrence that it is found in the project schematic by a cell symbol having input and outputs to generate the high level schematic. The process is then repeated for other predetermined cells.
In accordance with one aspect of the invention, the project schematic is represented by a project netlist of components and their interconnections, and wherein a cell netlist is generated for each of the cells to be searched in the project netlist. The cell netlists may be selected from a library of cell netlists or they may be generated through the creation of a cell schematic of a group of components and their interconnections.
In accordance with a further aspect of the invention, a netlist of the high level schematic may be generated to form a database for storage on a computer readable medium. The data includes cell names, signal labels for input and output signals between the cells, and cell schematic page numbers on which each signal is found. The data may further include a description of each cell function.
In accordance with another aspect of the invention, the process may further include dividing the project schematic into two or more subprojects, and generating individual project netlists for each subproject such that each subproject may be processed separately.
In accordance with a further aspect of this invention, a computer system is adapted to manipulate data from a high level schematic in one or more of the following ways: to sort the data by signal labels, to sort the data by inputs and outputs, to sort the data by schematic page number, to sort the data by cell names, to rename the signal labels, to describe the cell functions, to check the signals for errors, to modify the gate length data, to edit local pin segments, and to convert signal labels with identical labels to signal labels with unique labels.